Integrated circuits are fabricated using optical photolithography in which a circuit design or layout is transferred to a semiconductor substrate. In transferring the layout, a mask is generally created for each layer of the integrated circuit design that reproduces the patterns of that layer. To fabricate a particular layer of the design, the corresponding mask is placed over the substrate and optically projected onto the surface of the substrate. The photolithography process is typically followed by an etch process during which the underlying substrate not covered or masked by the photoresist pattern is etched away, leaving the desired pattern in the substrate. This process is then repeated for each layer of the design.
Photolithography processes are capable of reaching sub-micron resolutions, and each new process technology introduced enables the fabrication of smaller device sizes, densities, and geometries. The ability to print highly dense circuit layouts having minimal device sizes is dependent on the existence of a highly planar surface on which shapes from the mask is transferred. The planarity of the surface, in turn, is dependent upon the layout of the metal lines comprising a circuit.
In conventionally design circuit layouts, large open areas are left on the substrate between the nearest parallel electrically isolated metal lines, which include signal and power lines. The open areas are random in size and have a wide variety of dimensions. When a dielectric layer, such as an oxide, is subsequently deposited over the metal lines and open areas, the difference in height or thickness between the metal lines and the flat surfaces produce an altitude difference in the top surface of the dielectric layer. The process that attempts to minimize or eliminate the different altitudes of the top surface of the dielectric layer in different areas of the metal line design layout is called dielectric planarization.
Another method, known as the damascene process, to make metal lines is to use photolithography to define metal areas on the dielectric layer followed by etching to produce trenches partially through the dielectric layer first. Metal is then deposited to fill these trenches in such a way that the metal forms a blanket layer above the dielectric layer. This new metal is then eliminated to expose the inlaid metal lines by a combined mechanical and chemical polishing step. This entire process is known as metal planarization.
One popular planarization approach is to modify the metal line layout design by requiring standardize spacing between the various metal features (See for example U.S. Pat. No. 5,981,384). This standardization is accomplished by adding electrically isolated dummy metal features in the open spaces, and/or by increasing the size of existing electrically unisolated metal lines to reduce the spacing between nearest parallel metal lines to the standardize spacing.
FIG. 1 is a top view of a conventional metal line layout in which standardized spacing between the signal lines and dummy lines are employed to increase planarization. The layout 10 includes a series of metal signal lines 12 patterned in parallel and a grid of dummy lines 14 patterned in an open space adjacent to the signal lines 12. The dummy lines 14 are typically patterned in columns parallel to the signal lines 12 with uniform length and width. The first column is located a distance (D) from the signal lines 12, and the dummy lines 14 are separated from one another by a uniform spacing (Sd), where Sd=D. Once all the metal lines 12 and 14 have been patterned, a dielectric layer (not shown) is deposited over the substrate, resulting in substantial planarization due to the uniform spacing between the electrically isolated dummy metal lines 14 and the metal signal lines 14 beneath the dielectric layer.
Although the standardized spacing modification enhances planarization, patterning the dummy lines 14 too close to a signal line 12 increases capacitance between the dummy lines 14 and the signal line 12. The increased capacitance can affect the signal line 12 by slowing the transmission speed of signals, thereby degrading overall performance of the integrated circuit. However, patterning the dummy lines 14 too far away from the signal lines 12 may lead to unacceptable uniformity and planarization.
Accordingly, what is needed is an improved methodology for designing dummy lines that achieves an appropriate balance planarization and performance.